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FEATURES

x High-performance, E2CMOS 3.3-V & 5-V CPLD families

x Flexible architecture for rapid logic designs

— Excellent First-Time-FitTM and refit feature

— SpeedLockingTM performance for guaranteed fixed timing

— Central, input and output switch matrices for 100% routability and 100% pin-out retention

High speed

— 5.0ns tPD Commercial and 7.5ns tPD Industrial

— 182MHz fCNT

32 to 512 macrocells; 32 to 768 registers

44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages

Flexible architecture for a wide range of design styles

— D/T registers and latches

— Synchronous or asynchronous mode

— Dedicated input registers

— Programmable polarity

— Reset/ preset swapping

Advanced capabilities for easy system integration

— 3.3-V & 5-V JEDEC-compliant operations

— JTAG (IEEE 1149.1) compliant for boundary scan testing

— 3.3-V & 5-V JTAG in-system programming from Unlock PLD IC Lattice Semiconductor M4A5-64/32-10JC

— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)

— Safe for mixed supply voltage system designs

— Programmable pull-up or Bus-FriendlyTM inputs and I/Os

— Hot-socketing

— Programmable security bit

— Individual output slew rate control

Advanced E2CMOS process provides high-performance, cost-effective solutions

Supported by ispDesignEXPERTTM software for rapid logic development

— Supports HDL design methodologies with results optimized for ispMACH 4A

— Flexibility to adapt to user requirements

— Software partnerships that ensure customer success

— LatticePROTM software for in-system programmability support on PCs and automated test equipment

— Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General