Unlock Microcontroller PIC18F46K20 Program

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The HSPLL mode makes use of the HS mode oscillator for frequencies up to 16 MHz. A PLL then multiplies the oscillator output frequency by 4 to produce an internal clock frequency up to 64 MHz. The PLLEN bit of the OSCTUNE register is active only when the HFINTOSC is the primary clock and is not available in HSPLL oscillator mode.

The PLL is only available to the primary oscillator when the FOSC<3:0> Configuration bits are programmed for HSPLL mode (= 0110). The 4x frequency multiplier can be used with the internal oscillator block to produce faster device clock speeds than are normally possible with an internal oscillator if crack microcontroller pic18f4221 program.

When enabled, the PLL produces a clock speed of up to 64 MHz. Unlike HSPLL mode, the PLL is controlled through software. The PLLEN control bit of the OSCTUNE register is used to enable or disable the PLL operation when the HFINTOSC is used. The PLL is available when the device is configured to use the internal oscillator block as its primary clock source (FOSC<3:0> = 1001 or 1000). Additionally, the PLL will only function when the selected output frequency is either 8 MHz or 16 MHz (OSCCON<6:4> =111 or 110). If both of these conditions are not met, the PLL is disabled.

The PLLEN control bit is only functional in those internal oscillator modes where the PLL is available. In all other modes, it is forced to ‘0’ and is effectively unavailable. When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin, if used by the oscillator) will stop oscillating after extract Microcontroller pic18f2331 firmware.

In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the device clock. The Timer1 oscillator may also run in all power-managed modes if required to clock Timer1 or Timer3. In internal oscillator modes (INTOSC_RUN and INTOSC_IDLE), the internal oscillator block provides the device clock source. The 31 kHz LFINTOSC output can be used directly to provide the clock and may be enabled to support various special features, regardless of the power-managed mode (see Section 23.2 “Watchdog Timer (WDT)”, Section 2.10 “Two-Speed Clock Start-up Mode” and Section 2.11 “Fail- Safe Clock Monitor” for more information on WDT, Fail-Safe Clock Monitor and Two-Speed Start-up).

The HFINTOSC output at 16 MHz may be used directly to clock the device or may be divided down by the postscaler. The HFINTOSC output is disabled if the clock is provided directly from the LFINTOSC output. If the Sleep mode is selected, all clock sources are stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest current consumption of the device (only leakage currents).

Enabling any on-chip feature that will operate during Sleep will increase the current consumed during Sleep. The LFINTOSC is required to support WDT operation. The Timer1 oscillator may be operating to support a real-time clock. Other features may be operating that do not require a device clock source (i.e., SSP slave, PSP, INTn pins and others). Peripherals that may add significant current consumption are listed in Section 26.8 “DC Characteristics”.

Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applications. The delays ensure that the device is kept in Reset until the device power supply is stable under normal circumstances and the primary clock is operating and stable after Unlock Microcontroller.