We can Unlock Chip Microchip PIC24FJ256GB206 Flash Microcontrollers, please view the IC chip features for your reference:
High-Performance CPU
Analog Features:
Modified Harvard Architecture
Up to 16 MIPS Operation at 32 MHz
8 MHz Internal Oscillator
17-Bit x 17-Bit Single-Cycle Hardware Multiplier
32-Bit by 16-Bit Hardware Divider
16 x 16-Bit Working Register Array
C Compiler Optimized Instruction Set Architecture
· 10-Bit, up to 24-Channel Analog-to-Digital (A/D)
Converter at 500 ksps:
– Operation is possible in Sleep mode
– Band gap reference input feature
· Three Analog Comparators with Programmable
Input/Output Configuration
· Charge Time Measurement Unit (CTMU):
with Flexible Addressing modes
· Linear Program Memory Addressing, up to
12 Mbytes
· Data Memory Addressing, up to 16 Mbytes:
– 2K SFR space
– 30K linear data memory
– 66K extended data memory
– Remaining (from 16 Mbytes) memory (external) can be accessed using extended data Memory (EDS) and EPMP (EDS is divided into 32-Kbyte pages)
· Two Address Generation Units for Separate Read and Write Addressing of Data Memory
Power Management:
· On-Chip Voltage Regulator of 1.8V
· Switch between Clock Sources in Real Time
· Idle, Sleep and Doze modes with Fast Wake-up and
Two-Speed Start-up
· Run Mode: 800 mA/MIPS, 3.3V Typical
· Sleep mode Current Down to 20 mA, 3.3V Typical
· Standby Current with 32 kHz Oscillator: 22 mA, 3.3V
Peripheral Features (Continued):
· Peripheral Pin Select:
– Up to 44 available pins (100-pin devices)
· Three 3-Wire/4-Wire SPI modules (supports 4 Frame modes)
· Three I2C™ modules Supporting Multi-Master/Slave modes and 7-Bit/10-Bit Addressing
· Four UART modules:
– Supports RS-485, RS-232, LIN/J2602 protocols and IrDA®
· Five 16-Bit Timers/Counters with Programmable Prescaler
· Nine 16-Bit Capture Inputs, each with a Dedicated Time Base
· Nine 16-Bit Compare/PWM Outputs, each with a Dedicated Time Base
· Hardware Real-Time Clock and Calendar (RTCC)
· Enhanced Programmable Cyclic Redundancy Check (CRC) Generator
· Up to 5 External Interrupt Sources
C Compiler Optimized Instruction Set Architecture
· 10-Bit, up to 24-Channel Analog-to-Digital (A/D) Converter at 500 ksps:
– Operation is possible in Sleep mode
– Band gap reference input feature
· Three Analog Comparators with Programmable
Input/Output Configuration
· Charge Time Measurement Unit (CTMU): with Flexible Addressing modes
· Linear Program Memory Addressing, up to 12 Mbytes
· Data Memory Addressing, up to 16 Mbytes:
– 2K SFR space
– 30K linear data memory
– 66K extended data memory
· Two Address Generation Units for Separate Read and Write Addressing of Data Memory
Power Management:
· On-Chip Voltage Regulator of 1.8V
· Switch between Clock Sources in Real Time
· Idle, Sleep and Doze modes with Fast Wake-up and Two-Speed Start-up
· Run Mode: 800 mA/MIPS, 3.3V Typical
· Sleep mode Current Down to 20 mA, 3.3V Typical
· Standby Current with 32 kHz Oscillator: 22 mA, 3.3V
Universal Serial Bus Features:
· USB v2.0 On-The-Go (OTG) Compliant
· Dual Role Capable – Can act as either Host or Peripheral
· Low-Speed (1.5 Mbps) and Full-Speed (12 Mbps) USB Operation in Host mode
· Full-Speed USB Operation in Device mode
· High-Precision PLL for USB
· Supports up to 32 Endpoints (16 bidirectional):
– USB module can use the internal RAM location from 0x800 to 0xFFFF as USB endpoint buffers
· On-Chip USB Transceiver with Interface for Off-Chip Transceiver
· Supports Control, Interrupt, Isochronous and Bulk Transfers
· On-Chip Pull-up and Pull-Down Resistors
Peripheral Features:
· Enhanced Parallel Master Port/Parallel Slave Port (EPMP/PSP):
– Direct access from CPU with an Extended Data Space (EDS) interface
– 4, 8 and 16-bit wide data bus
– Up to 23 programmable address lines
– Up to 2 chip select lines
– Up to 2 Acknowledgement lines (one per chip select)
– Programmable address/data multiplexing
– Programmable address and data Wait states
– Programmable polarity on control signals with Flexible Addressing modes
· Linear Program Memory Addressing, up to 12 Mbytes
· Data Memory Addressing, up to 16 Mbytes:
– 2K SFR space
– 30K linear data memory
– 66K extended data memory
– Remaining (from 16 Mbytes) memory (external can be accessed using extended data Memory (EDS) and EPMP (EDS is divided into 32-Kbyte pages) before Unlock Chip Microchip PIC24FJ256GB206 Flash Microcontrollers
· Two Address Generation Units for Separate Read and Write Addressing of Data Memory
Power Management:
· On-Chip Voltage Regulator of 1.8V
· Switch between Clock Sources in Real Time
· Idle, Sleep and Doze modes with Fast Wake-up and Two-Speed Start-up
· Run Mode: 800 mA/MIPS, 3.3V Typical
· Sleep mode Current Down to 20 mA, 3.3V Typical
· Standby Current with 32 kHz Oscillator: 22 mA, 3.3V