Here by we would like to discuss the SoC FPGA Internal Structure, all fixed function modules included in the chip are shown in below picture.
These modules implement a complete dual-core ARM processor application processing unit and a large number of supporting interconnect buses, peripherals, memory and off-chip interfaces. The programmable logic section is shown at the very bottom of the diagram and is accessible through various system level interfaces. The organization has made new improvements to the programmable logic aspects of SoC FPGAs because fixed function components work even without programmable logic. This means that the processor system can “start” and then configure the programmable logic. Previous non-SoC methods required that the programmable logic be configured first before the processor could start. By reversing this sequence, programmable logic becomes a resource for the processor and it is easier to develop code in parallel with hardware development.
In fact, code developers can think of programmable logic in the SoC as a hardware resource that speeds up code segments that are too slow to implement on the processor. A design team member may focus their activities on creating hardware acceleration requested by the programmer, or the programmer may implement the hardware themselves. Either way, the algorithm becomes the focus of development for a variety of implementation options available.
The SoC approach seems to work best when multiple performance-oriented algorithms are running at the same time. One area of application where SoC FPGAs have been extremely successful is complex image processing. These algorithms can often be pipelined and/or parallelized, making them ideal for FPGA acceleration. If the processor also needs to handle high-bandwidth on-chip and off-chip traffic (possibly with high-speed serial interfaces and large off-chip buffer memory), additional hardware support to offload low-level tasks from the processor may also require a big dividend.