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The discrepancy in these definitions makes Replicate MC68HC11F1 Microcontroller Embedded Firmware difficult to specify an acquisition or lock time for a typical PLL. Therefore, the definitions for acquisition and lock times for this module are as follows:

Acquisition time, tACQ, is the time the PLL takes to reduce the error between the actual output frequency and the desired output frequency to less than the tracking mode entry tolerance TRK. Acquisition time is based on an initial frequency error, (fDES – fORIG)/fDES, of not more than 100%.

In automatic bandwidth control mode (see 9.4.2.3 Manual and Automatic PLL Bandwidth Modes), acquisition time expires when the ACQ bit becomes set in the PLL bandwidth control register (PBWC).

Lock time, tLOCK, is the time the PLL takes to reduce the error between the actual output frequency and the desired output frequency to less than the lock mode entry tolerance DLOCK. Lock time is based on an initial frequency error, (fDES – fORIG)/fDES, of not more than ±100%.

In automatic bandwidth control mode, lock time expires when the LOCK bit becomes set in the PLL bandwidth control register (PBWC).  Obviously, the acquisition and lock times can vary according to how large the frequency error is and may be shorter or longer in many cases.