Recover DSP IC Microchip dsPIC30F6010AT means restore the content of its heximal from both eeprom and flash, please check its features below:
High-Performance Modified RISC CPU:
· Modified Harvard architecture
· C compiler optimized instruction set architecture with flexible Addressing modes
· 83 base instructions
· 24-bit wide instructions, 16-bit wide data path
· 144 Kbytes on-chip Flash program space (Instruction words)
· 8 Kbytes of on-chip data RAM
· 4 Kbytes of nonvolatile data EEPROM
· Up to 30 MIPS operation:
– DC to 40 MHz external clock input
– 4 MHz-10 MHz oscillator input with PLL active (4x, 8x, 16x)
– 7.37 MHz internal RC with PLL active (4x, 8x, 16x)
· 44 interrupt sources:
– 5 external interrupt sources
· High-current sink/source I/O pins: 25 mA/25 mA
· Timer module with programmable prescaler:
– Five 16-bit timers/counters; optionally pair 16-bit timers into 32-bit timer modules
· 16-bit Capture input functions
· 16-bit Compare/PWM output functions
· 3-wire SPI modules (supports 4 Frame modes)
· I2CTM module supports Multi-Master/Slave mode and 7-bit/10-bit addressing
· 2 UART modules with FIFO Buffers
· 2 CAN modules, 2.0B compliant (dsPIC306010A)
· 1 CAN module, 2.0B compliant (dsPIC306015)
Motor Control PWM Module Features:
· 8 PWM output channels:
– Complementary or Independent Output modes
– Edge and Center-Aligned modes
· Dedicated time base
· Programmable output polarity
· Dead-Time control for Complementary mode
· Manual output control
· Trigger for A/D conversions
Quadrature Encoder Interface Module Features:
– 8 user selectable priority levels for each interrupt source
· 16 x 16-bit working register array
DSP Engine Features:
Phase A, Phase B and Index Pulse input 16-bit up/down position counter
Count direction status
Position Measurement (x2 and x4) mode
Programmable digital noise filters on inputs
Alternate 16-bit Timer/Counter mode
Dual data fetch
Interrupt on position counter rollover/underflow
Accumulator write-back for DSP operations
Modulo and Bit-Reversed Addressing modes
Two, 40-bit wide accumulators with optional saturation logic
Analog Features:
· 10-bit Analog-to-Digital Converter (ADC) with 4 S/H Inputs:
· 17-bit x 17-bit single-cycle hardware fractional