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Read Microcontroller PIC18F442 Firmware and extract it out from the flash and eeprom memory, the firmware will be presented in the format of binary or heximal, in order to do that we have to be able to get access to the memory cell and readout MCU the program and data from it;

Read Microcontroller PIC18F442 Firmware and extract it out from the flash and eeprom memory, the firmware will be presented in the format of binary or heximal, in order to do that we have to be able to get access to the memory cell and readout the program and data from it

There are three memory blocks in Enhanced MCU devices. These memory blocks are:

· Program Memory

· Data RAM

· Data EEPROM

Data and program memory use separate busses, which allows for concurrent access of these blocks.

Additional detailed information for FLASH program memory and Data EEPROM is provided in Section 5.0 and Section 6.0, respectively.

A 21-bit program counter is capable of addressing the 2-Mbyte program memory space. Accessing a location between the physically implemented memory and the 2-Mbyte address will cause a read of all ’0’s (a NOP instruction).

The PIC18F252 and PIC18F452 each have 32 Kbytes of FLASH memory, while the PIC18F242 and PIC18F442 have 16 Kbytes of FLASH. This means that PIC18FX52 devices can store up to 16K of single word instructions, and PIC18FX42 devices can store up to 8K of single word instructions before attack Microcontroller.

The RESET vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. Figure 4-1 shows the Program Memory Map for PIC18F242/442 devices and Figure 4-2 shows the Program Memory Map for PIC18F252/452 devices before microcontroller extraction.

The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a CALL or RCALL instruction is executed, or an interrupt is acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction.

PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions.

The stack operates as a 31-word by 21-bit RAM and a 5-bit stack pointer, with the stack pointer initialized to 00000b after all RESETS. There is no RAM associated with stack pointer 00000b. This is only a RESET value.

During aCALL type instruction, causing a push onto the stack, the stack pointer is first incremented and the RAM location pointed to by the stack pointer is written with the contents of the PC. During a RETURN type instruction, causing a pop from the stack, the contents of the RAM location pointed to by the STKPTR are transferred to the PC and then the stack pointer is decremented.