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Read Chip HOLTEK HT45R06 A/D Type 8-Bit OTP MCU

We can Read Chip HOLTEK HT45R06 A/D Type 8-Bit OTP MCU, please view the IC Chip features for your reference:

· Operating voltage: 2.2V~5.5V

(IDD<200mA, when fSYS=455kHz, VDD=+5V)

· Operating frequency: 400kHz~2MHz

455kHz: VDD=2.2V~5.5V

1MHz: VDD=2.4V~5.5V

2MHz: VDD=3.3V~5.5V

· 13 bidirectional I/O lines (PA, PB0~PB3, PD0)

· One interrupt input shared with an I/O line

· 8-bit programmable timer/event counter with

overflow interrupt and 7-stage prescaler

· On-chip crystal and RC oscillator

· Watchdog Timer

· 1024´14 program memory

· 64´8 data memory RAM

· Supports PFD for sound generation

General Description

The HT45R06 is an 8-bit high performance, RISC architecture microcontroller devices specifically designed for cost-effective multiple I/O control product applications.

The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, watchdog timer,

· HALT function and wake-up feature reduce power consumption

· Up to 2ms instruction cycle with 2MHz system clock at VDD=5V

· 4-level subroutine nesting

· 4 channels 8-bit resolution A/D converter

· PA with wake-up function

· Bit manipulation instruction

· 14-bit table read instruction

· 63 powerful instructions

· All instructions in 1 or 2 machine cycles

· Low voltage reset function

· Fast start-up: < 5ms (fSYS=455kHz, the RES is connected to VDD)

· 18-pin DIP/SOP, 20-pin SSOP packages buzzer driver, multi-channel A/D converter, Pulse Width

Modulation function, HALT and wake-up functions, enhance the versatility of these devices to suit a wide range of A/D application possibilities such as security systems, smoke detectors and smart tags.

Execution Flow

The system clock for the microcontroller is derived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme allows each instruction to be effectively executed in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction.

Program Counter – PC

The program counter (PC) controls the sequence in which the instructions stored in program ROM are executed and its contents specify full range of program memory. After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code.

When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC manages the program transfer by loading the address corresponding to each instruction.

The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction.

Otherwise proceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 locations. When a control transfer takes place, an additional dummy cycle is required.