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We can execute Microcomputer PIC16LF872 Secured Heximal Unlocking, please view the Microcomputer PIC16LF872 features for your reference:

We can microcomputer PIC16LF872 secured heximal unlocking, please view the microcomputer PIC16LF872 features for your reference:
To enable the serial port, SSPEN bit (SSPCON<5>) must be set. To reset or reconfigure SPI mode:
• Clear bit SSPEN
• Re-initialize the SSPCON register
• Set SSPEN bit
This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave in a serial port function, they must have their data direction bits (in the TRISC register) appropriately secured heximal. This is:
• SDI must have TRISC<7> set
• SDO must have TRISC<4> cleared
• SCK (Master mode) must have TRISC<6> cleared
• SCK (Slave mode) must have TRISC<6> set
• SS must have TRISA<5> set.
When initializing the SPI, several options need to be specified. This is done by secured heximal the appropriate control bits (SSPCON<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
Master mode (SCK is the clock output)
Slave mode (SCK is the clock input) if Microcomputer PIC16LF872 Secured Heximal Unlocking
Clock Polarity (Idle state of SCK)
Data Input Sample Phase (middle or end of data output time)
Clock Edge (output data on rising/falling edge of SCK)
Clock Rate (Master mode only)
Slave Select mode (Slave mode only)
The SSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR until the received data is ready.
Once the eight bits of data have been received, that byte is moved to the SSPBUF register. Then, the Buffer Full detect bit, BF (SSPSTAT<0>), and the interrupt flag bit, SSPIF, are set. This double-buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received after Microcomputer PIC16LF872 Secured Heximal Unlocking.
Any write to the SSPBUF register during transmission/reception of data will be ignored and the write collision detect bit, WCOL (SSPCON<7>), will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully when Unlock Microcontroller.