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Acquisition and lock times are designed to be as short as possible while still providing the highest possible stability of Duplicate MC68HC11K1 MCU Locked Program. These reaction times are not constant, however. Many factors directly and indirectly affect the acquisition time. The most critical parameter which affects the reaction times of the PLL is the reference frequency, fRDV.

This frequency is the input to the phase detector and controls how often the PLL makes corrections. For stability,
the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error which can be manipulated in the process of Duplicate MC68HC11K1 MCU Locked Program.
Therefore, the slower the reference the longer it takes to make these corrections. This parameter is also under user control via the choice of crystal frequency fXCLK.

Another critical parameter is the external filter capacitor. The PLL modifies the voltage on the VCO by adding or subtracting charge from this capacitor. Therefore, the rate at which the voltage changes for a given frequency error (thus change in charge) is proportional to the capacitor size.

The size of the capacitor also is related to the stability of the PLL. If the capacitor is too small, the PLL cannot make small enough adjustments to the voltage and the system cannot lock. If the capacitor is too large, the PLL may not be able to adjust the voltage in a reasonable time. .