Decrypt CPLD IC Xilinx XC9572-15PQ100C

Decrypt CPLD IC Xilinx XC9572-15PQ100C

Decrypt CPLD IC Xilinx XC9572-15PQ100C

We can Decrypt CPLD IC Xilinx XC9572-15PQ100C, below chip features for your reference:

Features

7.5 ns pin-to-pin logic delays on all pins

fCNT to 125 MHz

72 macrocells with 1,600 usable gates

Up to 72 user I/O pins

5V in-system programmable

Product Specification

Description

The XC9572 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 1,600 usable gates with propagation delays of 7.5 ns. See Figure 2 for the architecture overview.

– Endurance of 10,000 program/erase cycles

– Program/erase over full commercial voltage and temperature range

Enhanced pin-locking architecture to facilitate MCU reading

Flexible 36V18 Function Block

– 90 product terms drive any or all of 18 macrocells within Function Block

– Global and product term clocks, output enables, set and reset signals

Extensive IEEE Std 1149.1 boundary-scan (JTAG) support

Programmable power reduction mode in each macrocell

Slew rate control on individual outputs

User programmable ground pin capability by Reverse Engineering CPLD IC GAL16V8D

Extended pattern security features for design protection

High-drive 24 mA outputs

3.3V or 5V I/O capability

Advanced CMOS 5V FastFLASH™ technology

Supports parallel programming of more than one

XC9500 concurrently

Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP, and 100-pin TQFP packages

 

Power Management

Power dissipation can be reduced in the XC9572 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation.

Operating current for each design can be approximated for specific operating conditions using the following equation:

ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f

Where:

MCHP = Macrocells in high-performance mode

MCLP = Macrocells in low-power mode

MC = Total number of macrocells used f = Clock frequency (MHz)

Figure 1 shows a typical calculation for the XC9572 device.