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The programmed state of an EEPROM bit is logic 0. Erasing changes the state to a logic 1. Only EEPROM bytes in the non-protected blocks and EENVR register can be erased and then we can crack Microcontroller MC68HC08AZ60 eeprom memory.

Use the following procedure to erase a byte, block, or the entire EEPROM:
1. Configure EERAS1 and EERAS0 for byte, block, or bulk erase; set EELAT in EECR.(A)
2. Byte erase: write any data to the desired address.(B)
Block erase: write any data to an address within the desired block.(B)
Bulk erase: write any data to an address within the array.(B)
3. Set the EEPGM bit.(C)
Go to step 7 if AUTO is set.
4. Wait for a time: tEBYTE for byte erase; tEBLOCK for block erase; tEBULK for bulk erase.
5. Clear EEPGM bit.
6. Wait for a time, tEEFPV, for the erasing voltage to fall. Go to step 8 from Recover MCU.
7. Poll the EEPGM bit until it is cleared by the internal timer.(D)
8. Clear EELAT bits.(E)

Crack Microcontroller MC68HC08AZ60 Eeprom Memory

Setting the EELAT bit configures the address and data buses to latch data for erasing the array. Only valid EEPROM addresses will be latched. If EELAT is set, other writes to the EECR will be allowed after a valid EEPROM write in the process of MC68HC908QY4 CPU Embedded Firmware Cloning.

If more than one valid EEPROM writes occur, the last address and data will be latched, overriding the previous address and data. Once written data to the desired address, do not read EEPROM locations other than the written location. (Reading an EEPROM location returns the latched data, and causes the read address to be latched.) EENVR is not affected by block or bulk erase.

The EEPGM bit cannot be set if the EELAT bit is cleared or a non- valid EEPROM address is latched. This is to ensure proper programming sequence. Once EEPGM is set, do not read any EEPROM locations, otherwise the current erase cycle will be unsuccessful. When EEPGM is set, the erase mode cannot be changed, and the on-board erasing sequence will be activated in order to Break MC68HC908EY16 Microprocessor Protected Flash.

The delay time for the EEPGM bit to be cleared in AUTO mode is less than tEBYTE / tEBLOCK / tEBULK. However, on other MCUs, this delay time may be different. For forward compatibility, software should not make any dependency on this delay time which can applied for IC breaking.

Any attempt to clear both EEPGM and EELAT bits with a single instruction will only clear EEPGM. This is to allow time for removal of high voltage from the EEPROM array.