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The programmer’s model is shown in Figure 2-1 and consists of 16×16-bit working registers (W0 through W15), 2×40-bit accumulators (ACCA and ACCB), STATUS Register (SR), Data Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, DOEND, DCOUNT and RCOUNT) and Program Counter (PC). The working registers can act as Data, Address or Offset registers. All registers are memory mapped.

W0 acts as the W register for file register addressing. Some of these registers have a Shadow register associated with each of them, as shown in Figure 2-1. The Shadow register is used as a temporary holding register and can transfer its contents to or from its host register upon the occurrence of an event. None of the Shadow registers are accessible directly. The following rules apply for transfer of registers into and out of shadows.

· PUSH.S and POP.S

W0, W1, W2, W3, SR (DC, N, OV, Z and C bits only) are transferred.

· DO instruction

DOSTART, DOEND, DCOUNT shadows are pushed on loop start, and popped on loop end.

When a byte operation is performed on a working register, only the Least Significant Byte (LSB) of the target register is affected. However, a benefit of memory mapped working registers is that both the Least and Most Significant Bytes can be manipulated through byte wide data memory space accesses.

The dsPIC® DSC devices contain a software stack. W15 is the dedicated software Stack Pointer, and will be automatically modified by exception processing and subroutine calls and returns. However, W15 can be referenced by any instruction in the same manner as all other W registers. This simplifies the reading, writing and manipulation of the Stack Pointer (e.g., creating stack frames).

W15 is initialized to 0x0800 during a Reset. The user may reprogram the SP during initialization to any location within data space. W14 has been dedicated as a Stack Frame Pointer as defined by the LNK and ULNK instructions. However, W14 can be referenced by any instruction in the same manner as all other W registers.

The Program Counter is 23 bits wide. Bit 0 is always clear. Therefore, the PC can address up to 4M instruction words. The DSP engine consists of a high-speed 17-bit x 17-bit multiplier, a barrel shifter, and a 40-bit adder/subtracter (with two target accumulators, round and saturation logic).

The dsPIC30F devices have a single instruction flow which can execute either DSP or MCU instructions. Many of the hardware resources are shared between the DSP and MCU instructions. For example, the instruction set has both DSP and MCU multiply instructions which use the same hardware multiplier.

The DSP engine also has the capability to perform inherent accumulator-to-accumulator operations, which require no additional data. These instructions are ADD, SUB and NEG. The DSP engine has various options selected through various bits in the CPU Core Configuration register (CORCON), as listed below:

1.

Fractional or integer DSP multiply (IF).

2.

Signed or unsigned DSP multiply (US).

3.

Conventional or convergent rounding (RND).

4.

Automatic saturation on/off for ACCA (SATA).

5.

Automatic saturation on/off for ACCB (SATB).

6.

Automatic saturation on/off for writes to data memory (SATDW) before Crack MCU.

7.

Accumulator Saturation mode selection (ACCSAT).