Crack IC dsPIC30F4013 Heximal

Crack IC dsPIC30F4013 Heximal from the flash and eeprom memory, then copy firmware to other blank Microcontroller to make the perfect cloning units;

Crack IC dsPIC30F4013 Heximal

The core does not support a multi-stage instruction pipeline. However, a single-stage instruction prefetch mechanism is used, which accesses and partially decodes instructions a cycle ahead of execution, in order to maximize available execution time. Most instructions execute in a single cycle with certain exceptions.

The core features a vectored exception processing structure for traps and interrupts, with 62 independent vectors. The exceptions consist of up to 8 traps (of which 4 are reserved) and 54 interrupts. Each interrupt is prioritized based on a user-assigned priority between 1 and 7 (1 being the lowest priority and 7 being the highest), in conjunction with a predetermined ‘natural order’. Traps have fixed priorities ranging from 8 to 15.

The programmer’s model is shown in Figure 2-1 and consists of 16 x 16-bit working registers (W0 through W15), 2 x 40-bit accumulators (AccA and AccB), STATUS register (SR), Data Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, DOEND, DCOUNT and RCOUNT) and Program Counter (PC). The working registers can act as data, address or offset registers.

All registers are memory mapped. W0 acts as the W register for file register addressing. Some of these registers have a shadow register associated with each of them, as shown in Figure 2-1. The shadow register is used as a temporary holding register and can transfer its contents to or from its host register upon the occurrence of an event. None of the shadow registers are accessible directly.

The following rules apply for transfer of registers into and out of shadows.

· PUSH.S and POP.S W0, W1, W2, W3, SR (DC, N, OV, Z and C bits only) are transferred.

· DO instruction DOSTART, DOEND, DCOUNT shadows are pushed on loop start and popped on loop end.

When a byte operation is performed on a working register, only the Least Significant Byte of the target register is affected. However, a benefit of memory mapped working registers is that both the Least and Most Significant Bytes can be manipulated through byte-wide data memory space accesses.

The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17-bit x 17-bit multiplier/scaler is a 33-bit value, which is sign extended to 40 bits.

Integer data is inherently represented as a signed two’s complement value, where the MSB is defined as a sign bit. Generally speaking, the range of an N-bit two’s complement integer is -2N-1 to 2N-1 – 1. For a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7FFF) including ‘0’. For a 32-bit integer, the data range is – 2,147,483,648 (0x8000 0000) to 2,147,483,645 (0x7FFF FFFF).

When the multiplier is configured for fractional multiplication, the data is represented as a two’s complement fraction, where the MSB is defined as a sign bit and the radix point is implied to lie just after the sign bit (QX format). The range of an N-bit two’s complement fraction with this implied radix point is -1.0 to (1 – 21-N). For a 16-bit fraction, the Q15 data range is -1.0 (0x8000) to 0.999969482 (0x7FFF) including ‘0’ and has a precision of 3.01518×10-5. In Fractional mode, the 16×16 multiply operation generates a 1.31 product, which has a precision of 4.65661 x 10-10.

The same multiplier is used to support the MCU multiply instructions, which includes integer 16-bit signed, unsigned and mixed sign multiplies. The MUL instruction can be directed to use byte or word-sized operands. Byte operands direct a 16-bit result, and word operands direct a 32-bit result to the specified register(s) in the W array.

The data accumulator consists of a 40-bit adder/ (bit 39 overflow and saturation) subtracter with automatic sign extension logic. It can select one of two accumulators (A or B) as its preaccumulation source and post-accumulation destination. For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter prior to accumulation.