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Crack Chip PIC16LF720 Eeprom needs to reset the status of memory from locked to unlocked one, and then extract the heximal from its flash and eeprom;

Crack Chip PIC16LF720 Eeprom

The Power Control (PCON) register has two Status bits to indicate what type of Reset that last occurred. Bit 0 is BOR (Brown-out Reset). BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent Resets to see if BOR = 0, indicating that a Brown-out has occurred. The BOR Status bit is a “don’t care” and is not necessarily predictable if the brown-out circuit is disabled (BOREN<1:0> = 00 in the Configuration Word register).

Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on Reset and unaffected otherwise. The user must write a ‘1’ to this bit following a Power-on Reset. On a subsequent Reset, if POR is ‘0’, it will indicate that a Power-on Reset has occurred (i.e., VDD may have gone too low).

For more information, see Section 3.5 “Brown-Out Reset (BOR)”. Interrupts are disabled upon any device Reset. They are enabled by setting the following bits:

· GIE bit of the INTCON register

· Interrupt Enable bit(s) for the specific interrupt event(s)

· PEIE bit of the INTCON register (if the Interrupt

Enable bit of the interrupt event is contained in the PIE1 register)

The INTCON and PIR1 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual Interrupt Enable bits to faciliate the process of IC Extraction. The following events happen when an interrupt event occurs while the GIE bit is set:

· Current Program Counter (PC) is pushed onto the stack

· PC is loaded with the interrupt vector 0004h

The ISR determines the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous interrupts is 3 instruction cycles.

For asynchronous interrupts, the latency is 3 to 4 instruction cycles, depending on when the interrupt occurs. See Figure 4-2 for timing details. The external interrupt, INT pin, causes an asynchronous, edge-triggered interrupt. The INTEDG bit of the OPTION register determines on which edge the interrupt will occur.

When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector.

This interrupt is disabled by clearing the INTE bit of the INTCON register.