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External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the GEN bit is set to Copy MCU ST62T60 Flash Heximal . These interrupts allow the processor to exit from STOP mode.

The external interrupt polarity is selected through the IOR register.

External interrupts are linked to vectors #1 and # 2.

Interrupt requests on vector #1 can be configured either as edge or level-sensitive using the LES bit in the IOR Register.

Interrupt requests from vector #2 are always edge sensitive. The edge polarity can be configured us- ing the ESB bit in the IOR Register.

In edge-sensitive mode, a latch is set when a edge occurs on the interrupt source line and is cleared when the associated interrupt routine is started. So, an interrupt request can be stored until completion of the currently executing interrupt routine, before being processed through Embedded MCU P89C58 Flash Memory Decryption.

Copy MCU ST62T60 Flash Heximal

If several interrupt requests occurs before completion of the current in- terrupt routine, only the first request is stored. Storing of interrupt requests is not possible in level sensitive mode to ease the process of Microcontroller ST62T52 Dump reading. To be taken into account, the low level must be present on the interrupt pin when the MCU samples the line after instruction execution.