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CGMOUT is the clock output of the CGM. This signal goes to the SIM, which generates the MCU clocks. CGMOUT is a 50% duty cycle clock running at twice the bus frequency and it will help us to Copy MC68HC11KA4 Chip Flash Code. CGMOUT is software programmable to be either the oscillator output (CGMXCLK) divided by two or the VCO clock (CGMVCLK) divided by two.

PLLIE — PLL Interrupt Enable Bit

This read/write bit enables the PLL to generate an interrupt request when the LOCK bit toggles, setting the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear, PLLIE cannot be written and reads as 0. Reset clears the PLLIE bit.

1 = PLL interrupts enabled 0 = PLL interrupts disabled

PLLF — PLL Interrupt Flag Bit

This read-only bit is set whenever the LOCK bit toggles. PLLF generates an interrupt request if the PLLIE bit is set also. PLLF always reads as 0 when the AUTO bit in the PLL bandwidth control register (PBWC) is clear through the process of Unlock Freescale MC68HC11E9 Encrypted Heximal. The PLLF bit should be cleared by reading the PLL control register. Reset clears the PLLF bit.

Copy MC68HC11KA4 Chip Flash Code

1 = Change in lock condition

0 = No change in lock condition

The PLLF bit should not be inadvertently cleared. Any read or read- modify-write operation on the PLL control register clears the PLLF bit.

PLLON — PLL On Bit

This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). Reset sets this bit so that the loop can stabilize as the MCU is powering up in order to Unlock MC68HC08AZ32 MCU Eeprom Code.

1 = PLL on

0 = PLL off

BCS — Base Clock Select Bit

This read/write bit selects either the crystal oscillator output, CGMXCLK, or the VCO clock, CGMVCLK, as the source of the CGM output, CGMOUT. CGMOUT frequency is one-half the frequency of the selected clock. BCS cannot be set while the PLLON bit is clear. After toggling BCS, it may take up to three CGMXCLK and three CGMVCLK cycles to complete the transition from one source clock to the other by Break IC. During the transition, CGMOUT is held in stasis. Reset and the STOP instruction clear the BCS bit.

1 = CGMOUT driven by CGMVCLK/2 0 = CGMOUT driven by CGMXCLK/2