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We can Attack Motorola MC68HC11A1FN Microcontroller, please view the IC chip features for your reference:

1 Introduction

The MC68HC11A8, MC68HC11A1, and MC68HC11A0 high-performance microcontroller units (MCUs) are based on the M68HC11 Family. These high speed, low power consumption chips have multiplexed buses and a fully static design. The chips can operate at frequencies from 3 MHz to dc.

The three MCUs are created from the same masks; the only differences are the value stored in the CONFIG register, and whether or not the ROM or EEPROM is tested and guaranteed. For detailed information about specific characteristics of these MCUs, refer to the M68HC11 Reference

Manual (M68HC11RM/AD).

1.1 Features

· M68HC11 CPU

· Power Saving STOP and WAIT Modes

· 8 Kbytes ROM

· 512 Bytes of On-Chip EEPROM

· 256 Bytes of On-Chip RAM (All Saved During Standby)

· 16-Bit Timer System

— 3 Input Capture Channels

— 5 Output Compare Channels

· 8-Bit Pulse Accumulator

· Real-Time Interrupt Circuit

· Computer Operating Properly (COP) Watchdog System

· Synchronous Serial Peripheral Interface (SPI)

· Asynchronous Nonreturn to Zero (NRZ) Serial Communications Interface (SCI)

· 8-Channel, 8-Bit Analog-to-Digital (A/D) Converter

· 38 General-Purpose Input/Output (I/O) Pins

— 15 Bidirectional I/O Pins

— 11 Input-Only Pins and 12 Output-Only Pins (Eight Output-Only Pins in 48-Pin Package)

· Available in 48-Pin Dual In-Line Package (DIP) or 52-Pin Plastic Leaded Chip Carrier (PLCC)

In single-chip operating mode, the MC68HC11A8 is a monolithic microcontroller without external address or data buses with these features can help to Attack Motorola MC68HC11A1FN Microcontroller.

In expanded multiplexed operating mode, the MCU can access a 64 Kbyte address space. The space includes the same on-chip memory addresses used for single-chip mode plus external peripheral and memory devices. The expansion bus is made up of ports B and C and control signals AS and R/W.

The address, R/W, and AS signals are active and valid for all bus cycles including accesses to internal memory locations. The following figure illustrates a recommended method of demultiplexing low-order addresses from data at port C.