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The active reset from internal source is a quite useful mechanism for Freescale MC68HC908RK2 Microprocessor Memory Breaking:

Freescale MC68HC908RK2 Microprocessor Memory Breaking

All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow for resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles.

An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI, or POR. See Figure 8-6. Note that for LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles, during which the SIM forces the RST pin low to faciliate the process of Crack Philip Microcomputer P87C54 Eeprom Memory Code. The internal reset signal then follows the sequence from the falling edge of RST as shown in below Figure.

Internal reset timing

The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU.  When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power-on has occurred in the process of MCU Recovering.

The external reset pin (RST) is held low while the SIM counter counts out 4096 CGMXCLK cycles. 64 CGMXCLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur.

At power-on, the following events occur:

A POR pulse is generated

The internal reset signal is asserted

The SIM enables CGMOUT

Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow the oscillator to stabilize Freescale MC68HC908GT16 CPU Unlocking.

The RST pin is driven low during the oscillator stabilization time
The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared.