IC Crack Service | MCU Crack Service | Microcontroller Unlock Service Provider

Hardware watchdog timer can get involved in the NXP P89C664 Microcontroller Protected Firmware Unlocking, since ONE-TIME ENABLED WITH RESET-OUT FOR P89C664, The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer reset (WDTRST) SFR. The WDT is disabled at reset.

To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset).

When WDT overflows, it will drive an output reset HIGH pulse at the RST-pin.  To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow.

NXP P89C664 Microcontroller Protected Firmware Unlocking

The 14-bit counter overflows when it reaches 16383 (3FFFH) and this will reset the device. When using the WDT, a 1Kohm resistor must be inserted between RST of the device and the Power On Reset circuitry from NXP P89C664 Microcontroller Protected Firmware Unlocking. When WDT is enabled, it will increment every machine cycle while the oscillator is running.

This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT, the user must write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the reset pin.

The RESET pulse duration is 98 ´ TOSC, where TOSC = 1/fOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.