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Clone ST Microcomputer ST7FMC1K4BC Source Code from its embedded flash and eeprom needs to understand the 8-bit Condition Code register operational functionality since it control the programming performance of this microcomputer, below we will introduce the Condition Code register structure and size:

The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP in- structions.

These bits can be individually tested and/or con- trolled by specific instructions.

Arithmetic Management Bits

Bit 4 = H Half carry.

This bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions when Clone ST Microcomputer ST7FMC1K4BC Source Code.

0: No half carry has occurred. 1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruc- tion. The H bit is useful in BCD arithmetic subrou- tines.

Bit 2 = N Negative.

This bit is set and cleared by hardware. It is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. It’s a copy of the re- sult 7th bit.

0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions after Clone ST Microcomputer ST7FMC1K4BC Source Code.

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero.

0: The result of the last operation is different from zero.

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test instructions.

Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and soft- ware. It indicates an overflow or an underflow has occurred during the last arithmetic operation.

0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred when CLONE IC.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.