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The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.
The device has the following clock source options, selectable by Flash Fuse Bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules.
The various choices for each clocking option is given in the following sections. When the CPU wakes up from Power-down or Power-save to recover atmega64 mcu embedded heximal, the selected clock source is used to time the start-up, ensuring stable Oscillator operation before instruction execution starts.
When the CPU starts from reset, there is as an additional delay allowing the power to reach a stable level before com- mencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time by atmega64l microprocessor flash software restoration. The number of WDT Oscillator cycles used for each time-out is shown in Table 3.
The frequency of the Watchdog Oscillator is voltage dependent as shown in “ATmega8 Typical Characteristics – TA = -40°C to 85°C”. The device is shipped with CKSEL = “0001” and SUT = “10” (1MHz Internal RC Oscillator, slowly rising power).