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The system status and configuration module (SSCM) provides central device functionality. The SSCM includes these features:

System configuration and status

Memory sizes/status

Device mode and security status

Determine boot vector

Search code flash for bootable sector

DMA status

Debug status port enable and selection which can be used for microcontroller spc560p44l5 flash memory unlocking

Bus and peripheral abort enable/disable

The following list summarizes the system clock and clock generation on the SPC560P34/SPC560P40:

Lock detect circuitry continuously monitors lock status

Loss of clock (LOC) detection for PLL outputs

Programmable output clock divider (¸1, ¸2, ¸4, ¸8)

FlexPWM module and eTimer module running at the same frequency as the e200z0h core

Internal 16 MHz RC oscillator for rapid start-up and safe mode: supports frequency trimming by user application

The FMPLL allows the user to generate high speed system clocks from a 4–40 MHz input clock. Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication factor, output clock divider ratio are all software configurable.

The FMPLL has the following major features:

Input clock frequency: 4–40 MHz

Maximum output frequency: 64 MHz

Voltage controlled oscillator (VCO)—frequency 256–512 MHz

Reduced frequency divider (RFD) for reduced frequency operation without forcing the FMPLL to relock in the process of recover spc560p50l3 mcu flash memory program;

Frequency-modulated PLL

Modulation enabled/disabled through software

Triangle wave modulation

Programmable modulation depth (±0.25% to ±4% deviation from center frequency): programmable modulation frequency dependent on reference frequency.

Self-clocked mode (SCM) operation