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The AT89C5130A/31A-M PLL is used to generate internal high frequency clock (the USB Clock) synchronized with an external low-frequency (the Peripheral Clock). The PLL clock is used to generate the USB interface clock. Figure 5-3 shows the internal structure of the PLL.

The PFLD block is the Phase Frequency Comparator and Lock Detector. This block makes the comparison between the reference clock coming from the N divider and the reverse clock coming from the R divider and generates some pulses on the Up or Down signal depending on the edge position of the reverse clock if extract microcontroller pic16f526 binary.

The PLLEN bit in PLLCON register is used to enable the clock generation. When the PLL is locked, the bit PLOCK in PLLCON register (see Figure 5-3) is set.

The CHP block is the Charge Pump that generates the voltage reference for the VCO by injecting or extracting charges from the external filter connected on PLLF pin (see Figure 5-4). Value of the filter components are detailed in the Section “DC Characteristics”.

The VCO block is the Voltage Controlled Oscillator controlled by the voltage VREF produced by the charge pump. It generates a square wave signal: the PLL clock when Unlock MCU pic12f519 binary.

The Special Function Registers (SFRs) of the AT89C5130A/31A-M fall into the following categories:

· C51 core registers: ACC, B, DPH, DPL, PSW, SP

· I/O port registers: P0, P1, P2, P3, P4

· Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H

· Serial I/O port registers: SADDR, SADEN, SBUF, SCON

· PCA (Programmable Counter Array) registers: CCON, CMOD, CCAPMx, CL, CH, CCAPxH, CCAPxL (x: 0 to 4)

· Power and clock control registers: PCON

· Hardware Watchdog Timer registers: WDTRST, WDTPRG

· Interrupt system registers: IEN0, IPL0, IPH0, IEN1, IPL1, IPH1 after Unlock MCU

· Keyboard Interface registers: KBE, KBF, KBLS

· LED register: LEDCON

· Two Wire Interface (TWI) registers: SSCON, SSCS, SSDAT, SSADR

· Serial Port Interface (SPI) registers: SPCON, SPSTA, SPDAT

· USB registers: Uxxx (17 registers)

· PLL registers: PLLCON, PLLDIV

· BRG (Baud Rate Generator) registers: BRL, BDRCON

· Flash register: FCON (FCON access is reserved for the Flash API and ISP software)

· EEPROM register: EECON

· Others: AUXR, AUXR1, CKCON0, CKCON1

INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it.

In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is ‘0’ or ‘1’ on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.

The AT89C5130A/31A-M implement 16/ 32 Kbytes of on-chip program/code memory. Figure 8-1 shows the split of internal and external program/code memory spaces depending on the product.

The Flash memory increases EPROM and ROM functionality by in-circuit electrical erasure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing Flash cells is generated on-chip using the standard VDD voltage.

Thus, the Flash Memory can be programmed using only one voltage and allows In- application Software Programming commonly known as IAP. Hardware programming mode is also available using specific programming tool.

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